FIG. 1 is a block diagram of a conventional dynamic random access memory (DRAM) having 65,536 (64K) memory cells configured in 256 rows along 256 columns. Externally supplied address signals are used to select one of the memory cells to store or retrieve data.
DRAM 1 includes a square array of memory cells 25 connected at crossovers of bit and word lines arranged in 256 rows and 256 columns. Row and Column Address Buffer 21 sequentially receives an eight-bit row address signal and an eight-bit column address signal from address input terminals A.sub.1 -A.sub.8. The eight-bit row address signal is supplied to Row Decoder 22 which decodes the signal to select one of the 256 word lines. The word lines receive the decoded row address signal from Row Decoder 22 for selecting memory cells connected to the selected word line.
The bit lines of Memory Cell Array 25 are connected to bit line sense amplifiers and input/output gates of Sense Refresh Amplifier and I/O Control 24. Data to be stored into a selected memory cell is received into Data In Buffer 26 which supplies data input signals to Sense Refresh Amplifier and I/O Control 24.
Column decoder 23 decodes the 8-bit column address signal from Row & Column Buffer 21 to supply a decoded column address signal to Sense Refresh Amplifier and I/O Control 24 for selecting one of the sense amplifiers. A data signal from the selected sense amplifier of Memory Cell Array 25 is supplied to Data Out Buffer 27 through Sense Refresh Amplifier and I/O Control 24.
Power, data and control signals are received at power input terminals 2 and 3, Row Address Strobe (RAS) input terminal 4, Column Address Strobe (CAS) terminal 8, and Write Enable Terminal W. Clock Generator Circuit 10 receives RAS and CAS signals to supply a first clock signal .phi..sub.1 to Column Decoder 23 and a second clock signal .phi..sub.2 to AND gate 28. AND gate 28 receives clock signal .phi..sub.2 and a write enable signal for supplying data strobe signals to Data In Buffer 26 and Data Out Buffer 27.
In operation, clock generator 10 RAS and CAS signals are supplied from a central processing unit (CPU) not shown. In response to the RAS and CAS signals, clock generator circuit 10 develops clock signals .phi..sub.1 and .phi..sub.2. During normal read/write operations of the DRAM, address signal buffer 21 receives 16 bits of address signal data in two sequential 8 bit bytes at external address signal input terminals A.sub.1 -A.sub.8. The sixteen bit address signal includes an eight bit row address signal portion and an eight bit column address signal portion.
Address signal buffer 21 supplies the row and column bytes of address signal data on a time multiplex basis to row decoder 22 and column decoder 23. Row decoder 22 and column decoder 23 decode the internal address signals A.sub.1 -A.sub.8 and apply the decoded signals to memory cell array 25 and I/O controller 24. In response to the row address signal data supplied to row decoder 22, a row of memory cells is selected from memory cell array 25. Column address signal data applied to column decoder 23 enables reading from or writing to the selected column of memory cells. The memory cell of memory cell array 25 in the selected row and column can then be accessed for data storage or retrieval.
Data to be stored in a memory cell is received as a data signal at the Data Input terminal and stored in buffer 26. In response to a first write enable signal W and a clock signal .phi..sub.2, data is transferred from buffer 26 to I/O signal controller 24. Column decoder 23 is enabled by clock signal .phi..sub.1 to supply data to memory cells in the selected column of the memory cell array. However, because only memory cells in the row selected by row decoder 22 are enabled, data is stored only in the memory cell having the selected row and column address signals.
FIG. 2 is a block diagram showing the memory cell array of the DRAM in further detail. Each memory cell comprises a data storage capacitor connected through a gate transistor to one bit line of a bit line pair. The gate electrodes of the gate transistors are connected to the word lines which, in turn, are connected to the Row Decoder 22. Sense amplifiers S/A receive decoded address signals from Column Decoder 23 for amplifying data signals present on the bit line pairs.
In response to the row address signal, row decoder 22 applies a high output level select signal to a selected one of 256 word lines WL. The select signal causes the gate transistors connected to the selected word line WL to become conductive, allowing a transfer of charge between the associated data storage capacitor and the associated bit line pair BL. During a read operation, sense amplifiers S/A are activated to respond to the charge read out from the storage capacitors of the selected row to the bit line pairs. In response to the column address signal, column decoder 23 activates a transfer gate (not shown) in a selected column to transfer the amplified data signal from the selected bit line pair BL to Data Output Buffer 27 (FIG. 1). The data is supplied at a data output terminal in response to signal clock .phi..sub.2.
During a write operation, data from Data In Buffer 26 is supplied to the sense amplifier of the selected column in response to the column address signal applied to column decoder 23. Row Decoder 22 provides a high level signal to the selected word line WL in response to the row address signal, turning on the associated gate transistors of the selected row. With the transistor turned on, a data charge is transferred from the bit lines to the storage capacitor of the selected column. Because no data is applied to the non-selected sense amplifiers, data stored in memory cells of non-selected columns is refreshed but not altered.
The function of the address signal decoders, i.e., the row and column decoders, is to receive binary address signal data and, in response, to provide an output on a corresponding output line. As described, the row decoder provides a high level signal to a word line to cause gate transistors in the associated row to become conductive. The column decoder activates a selected gate to connect a bit line pair to the memory I/O buffer. A simplified schematic diagram of a conventional "rectangular" 8 in--256 out address signal decoder is shown in FIG. 3.
Referring to FIG. 3, a rectangular decoder includes a linear array of AND gates, each having a number of inputs equal to the number of bit signals to be decoded. The number of AND gates is equal to the number of output address signal lines to be selected. The decoder includes inverting buffer amplifiers supplying true address signals to true address signal line 13 and inverted address signals to inverted address signal line 14. In the example of FIG. 3, sixteen inverting amplifiers 11 and 12 provide true and inverted address signals a.sub.0 -a.sub.7 to address signal lines 13 and 14. Each of 256 AND gates 16 has eight input terminals for receiving different combinations of the true and inverted address signals a.sub.0 -a.sub.7.
In operation, an 8 bit address signal a.sub.0 -a.sub.7 is applied to a buffer stage including inverting amplifiers 11 and 12 to supply buffered true address signals to lines 13 and inverted address signals to lines 14. Each of the eight inputs 15 of AND gates 16 is connected to either the true or complemented address signal line for each of the 8 address signal bits a.sub.0 -a.sub.7. Output 17 from the 256 AND gates provide mutually exclusive output signals Y.sub.0 -Y.sub.255 in response to the address signal data supplied to the buffer inverter amplifiers.
One problem with the rectangular address signal decoder configuration shown in FIG. 3 arises from the complexity of the 8 input AND gates required to implement the decoder function and from the number and configuration of connections required. Further, drivability problems arise since each address signal line "fans out" to drive 128 AND gates.
Another drawback of the rectangular decoder shown in FIG. 3 results from increased spacing or "pitch" between select output lines 17 caused by the number of devices required to implement the 8 input AND gates 16. A rectangular memory address signal decoder implemented as shown in FIG. 3 has a large output line pitch in comparison with the width of the memory cell array.
To minimize the number of gate inputs, memory devices have been implemented using multiple stages of address signal decoding. A predecode circuit is responsive to the data bits of an original input address signal for supplying subdecoded address signals. A plurality of decoder units is responsive to different combinations of the original input address signal bits and the subdecoded signals to provide selector output signals onto corresponding output lines. A representative circuit for decoding an address signal is described in Hoshi, U.S. Pat. No. 4,777,390. However, these decoding circuits still require decoder logic gates having three or more inputs to provide decoded output signals.
An alternative address signal decoder arrangement is shown in FIGS. 4 and 5. FIG. 4 is a schematic diagram of a subdecoder of a first dual-tree type address signal decoders for supplying a first group of subfunction signals f.sub.0 -f.sub.15 in response to address signals a.sub.0 -a.sub.3. A second subdecoder receives address signals a.sub.4 -a.sub.7 for supplying a second group of subfunction signals f.sub.16 -f.sub.31. Each subdecoder comprises an array of sixteen AND gates arranged in a 4.times.4 matrix.
The first and second groups of subfunction signals are applied through respective amplifiers to an array decoder comprising a 16.times.16 matrix of AND gates as shown in FIG. 5. In response to the two groups of subfunction signals, the array decoder supplies 256 mutually exclusive select signals representing the decoded address signals.
The dual-tree decoder minimizes the number of inputs to each logic element, thereby eliminating the requirement for AND gates having more than two-inputs. However, each subfunction signal must drive multiple AND gates which introduces drivability problems and increases decoding propagation delays. Further, complex signal routing paths are required to distribute the subfunction signals to and within the decoder and to supply decoder output signals to the word lines of an associated memory cell array.
Further, subdecoding type address signal decoders mismatch the pitch of decoder gate output lines and the nominal pitch of word lines of a memory array. While a DRAM memory cell array requires a single gate transistor in combination with a storage capacitor for each cell, the multiple input decoder gates associated with each word line require multiple transistors. Accordingly, the decoder circuitry must be wider than the associated memory cell array. A similar problem is present in a Static RAM (SRAM) memory cell array. Although an array of SRAM memory cells may be wider than a comparable array of DRAM cells, the distance between SRAM memory cells is less than the distance between decoder gate output lines. That is, the pitch of the SRAM word lines is less than the pitch of the corresponding decoder output lines.
Alternatively, the decoder gates must be formed in several rows, complicating signal routing to and from the gates. Forming an address signal decoder using several rows of gates requires that input and output gates be routed across or around adjacent circuits For example, FIG. 6 is a diagram of a single-poly, double-metal CMOS integrated circuit. A gate array includes rows 30 and 40 of serially connected p-type and n-type transistors 32 and 42. A pair of adjacent transistor rows including p-type row 30 and n-type row 40 form a bench 50. A pair of adjacent transistors, an n-type and p-type, form a basic cell 52.
P-type transistor 32, formed in p-type row 30, includes a polysilicon gate 34 separating first and second source drain regions 36 and 38. Similarly, n-type transistor 42 includes first and second source/drain regions 46 and 48 on opposite sides of polysilicon gate 44. Interconnect wiring is provided in routing channel 60 along metal-1 routing tracks 62 to provide conductivity in a row direction and metal-2 routing tracks 64 to provide conductivity in a column direction. The designations metal-1 and metal-2 refer to respective lower and upper metal conductive layers formed during sequential circuit fabrication processing steps. The metal-1 layer is insulated from the metal-2 layer by an interlayer insulator. Typically, localized internal wiring within or among adjacent basic cells uses metal-1 interconnections; metal-2 routings provide interbench connectivity. V.sub.cc bus 54 and V.sub.ss bus 56 use metal-1 routings to provide power in a row direction over the lower metalization layer to transistors of each basic cell.
A cross-section of a typical CMOS device is shown in FIG. 7. P-type substrate 70 includes a p-well 72 and an n-well 74. A p-type field effect- transistor (FET) is formed on the surface of substrate 70 in the region of p-well 72. The p-type FET includes a gate electrode insulator 76 formed on the surface of the substrate. A polycide gate electrode is formed on gate electrode insulator 76 and includes a gate electrode lower layer 78 made of polysilicon and an upper metal silicide layer made of, for example, tungsten silicide Gate electrode 78, 80 is formed above a channel region with gate electrode sidewall insulators 82 formed on the sidewalls of the gate electrode.
To avoid hot carrier generation, the p-type FET includes a lightly doped drain (LDD) structure with a low concentration n.sup.- region 84 formed under sidewall insulators 82 and a higher concentration n.sup.+ region 86 formed distant from the gate electrode.
An n-type FET is formed in n-well region 74 of substrate 70, and includes a polycide gate electrode having a polysilicon lower layer 90 and a metal silicide upper layer 92. Sidewall insulators 93 are formed on opposite sidewalls of the gate electrode. Source/drain regions 96 are formed in the upper surface of the substrate on opposite sides of a channel region below the gate electrode.
Inter-element isolation regions 94 electrically isolate the FETs along the surface of the substrate. An interlayer insulator 98 is formed over the inter-element isolation regions and the gate electrodes. A lower metal-1 routing includes a first polycide interconnect layer 100 extending into a contact hole through interlayer insulation 98 to form a source/drain electrode. Metal-1 polycide interconnection layer 100 includes a lower metal nitride layer 106 and an upper metal polycide layer 108. The metal nitride layer may include, for example, titanium nitride. Similar metal-1 polycide layers 102 and 104 form source/drain electrodes for the p and n type FETs.
An interlayer insulator 98 is formed over metal-1 polycide interconnection layer 100, 102 and 104. A metal-2 layer 110 includes a metal polycide and is formed on interlayer insulation 98. Conductivity between the metal-1 and metal-2 layers is provided through contact hole 112, the metal layers coming into contact at interface 114.
In a typical gate layout as shown in FIG. 8, a logic gate device comprises four adjacent basic cells. The cells include transistors formed in N diffusion region 116 and p diffusion region 117. Source/drain regions of the transistors are formed in the diffusion regions on opposite sides of polysilicon gate electrodes 120-126. Metal-1 routings 127 connect underlying substrate diffusion regions 116 and 117 and polysilicon gate electrodes 120-126, and overlying metal-2 routings 128.
As shown in FIG. 8, metal-2 output 128 from the logic gate device uses at least one of the four possible routing tracks. Thus, only 25% of the available metal-2 routing tracks are used. To increase decoder output line density to be equal to the density of the memory cell array, outputs must be provided along each metal-2 routing track of the decoder. That is, the pitch of the decoder output lines 128-134 must be equal to the pitch of the word lines of the associated memory cell array as shown in FIG. 9. However, since four basic cells are required per gate, the number of transistors required to implement such a decoder will not fit within a basic 256 cell bench without stacking multiple benches. If multiple benches are stacked, insufficient unused metal-2 routing remain to provide the required number of signal input lines to each logic device. The number of metal-1 routings available in each bench are also limited due to the requirements for intracell metal-1 connectivity. Therefore, alternate benches are dedicated to provide the additional metal-1 connectivity to the logic devices formed in adjacent benches. However, this results in decreased integration density.
Accordingly, an object of the invention is to provide a decoder structure compatible with dense memory cell array layout criteria in which 100% of all metal-2 routing tracks are utilized without sacrificing decoder integration density.
Another object of the invention is to make the inputs of all gates accessible without interfering with metal-2 tracks required by outputs from the decoder
A still further object of the invention is to minimize the number of inputs provided to logic gates of a decoder within a critical area beneath a memory cell array.